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1/30 voltage detector with delay time adjustable XC6129 series general description XC6129 series is an ultra small highly accurate voltage detector with external capacitor type delay function. the device includes a highly accurate reference voltage source, manufactured using cmos process and laser trimming technology, it maintains low power consumption and high accura cy. the device includes the built-in delay circuit. a release delay time or detect delay time can be set freely by connecting an external delay capacitor to cd pin. there are two kinds of the output configuration for the XC6129 such as cmos or n-channel open drain. the series has a function to prevent an indefinite operation. therefore, when the input pin voltage is under minimum operating voltage, the function controls an output pin voltage in the indefinite operation less than 0.4v (max.). also, the series allows a choic e of an output logic when detection; therefor e, it is suitable for various electric devices using microcontrollers. ultra small package uspn-4 and ssot-24 (standard) are ideally suited for small design of portable devices and high densely mounting applications. features high accuracy : 0.8 (ta=25 ) temperature characteristic : 50ppm/ (typ.) hysteresis width : v df x5% (typ.) or less than v df x1% low power consumption : 0.42 a typ. (at detect, v df =2.7v) 0.58 a typ. (at release, v df =2.7v) detect voltage options : 1.5v 5.5v (0.1v increments) operating voltage range : 1.3v 6.0v output configuration : cmos or n-channel open drain output logic : active high or active low release delay time : 13.9ms (cd=0.01 f, r p =2m ? ) detect delay time : 17.9ms (cd=0.01 f, r n = 2 m ? ) manual reset input : when cd pin is ?l? level, detect state operating ambient temperature : -40 +85 packages : uspn-4, ssot-24 environmentally friendly : eu rohs compliant, pb free etr0222-002 a pplications microprocessor logic circuit reset circuitry battery check charge voltage monitors memory battery back-up switch circuits system power on reset power failure detection circuits delay circuit typical application circuits typical performance characteristics XC6129 100 120 140 160 180 200 -50 -25 0 25 50 75 100 ambient temperature : ta ( ) release delay time : t dr (ms) v in =v df 0.9v v df 1.1v cd=0.1f (t dr =139ms)
2/30 XC6129 series block diagrams 1) XC6129c series (type a/b/c/d/e/f) 2) XC6129c series (type g/j/l) resetb vre f v in cd/ mrb v ss m1 m2 m3 m4 comparator r 1 r 2 rp rn delay/mr control bl ock reset vre f v in cd/ mrb v ss m1 m2 m3 m4 comparator r 1 r 2 rp rn delay/mr control bl ock * diodes inside the circuits are esd protection diodes and parasitic diodes.
3/30 XC6129 series block diagrams * diodes inside the circuits are esd protection diodes and parasitic diodes. 3) XC6129n series (type a/c/e) 4) XC6129n series (type g/j/l) resetb vre f v in cd/ mrb v ss m1 m2 m3 comparator r 1 r 2 rp rn delay/mr control bl ock reset vre f v in cd/ mrb v ss m1 m2 m3 comparator r 1 r 2 rp rn delay/mr control bl ock
4/30 XC6129 series product classification designator item symbol description output configuration c cmos output n nch open drain output ? detect voltage 15~55 e.g. 1.8v =1, =8 type a refer to selection guide b c d e f g j l ?- (*1) packages (order unit) nr-g ssot-24 (3,000/reel) 7r-g uspn-4 (5,000/reel) (*1) the ?-g? suffix denotes halogen and antimony free as well as being fully eu rohs compliant. type resetb/reset output hysteresis width release delay detect delay undefined operation protect a reset active low 5% (typ.) yes no no b yes (*2) c no yes no d yes (*2) e yes yes no f yes (*2) g reset active high yes no no j no yes l yes yes (*2) only supported with cmos output. ordering information XC6129 ?????- (*1) selection guide
5/30 XC6129 series pin configuration pin assignment pin number pin name functions ssot-24 uspn-4 1 4 v in power input 2 3 v ss ground 3 2 cd/mrb adjustable pin for delaytime /manual reset 4 1 resetb reset output (active low) (*1) reset reset output (active high) (*2) (*1) type a f (refer to the in ordering information table) (*2) type g m (refer to the in ordering information table) ssot-24 (top view) uspn-4 (bottom view)
6/30 XC6129 series function chart pin name signal status cd/mrb l forced reset h release open normal operation refer to the table below. 1) output logic: active low function chart v in v cd//mrb transition of v resetb condition v in R v df +v hys v cd/mrb Q v mrl reset (low level) (*1) v cd/mrb R v mrh release (high level) (*2) v in Q v df v cd/mrb Q v mrl reset (low level) (*1) v cd/mrb R v mrh undefined (*3) 2) output logic: active high function chart v in v cd/mrb transition of v reset condition v in R v df +v hys v cd/mrb Q v mrl reset (high level) (*2) v cd/mrb R v mrh release (low level) (*1) v in Q v df v cd/mrb Q v mrl reset (high level) (*2) v cd/mrb R v mrh undefined (*3) (* 1) cmos output: v in 0.1 or less, n-ch open drain output, pull-up voltage 0.1 or less. (* 2) cmos output: v in 0.9 or higher, n-ch open drain output, pull-up voltage 0.9 or higher. (* 3) refer to the operating description below.
7/30 XC6129 series absolute maximum ratings parameter symbol ratings units input voltage v in -0.3 +6.5 v output current XC6129c (*1) i rbout i rout 50 ma XC6129n (*2) 50 output voltage XC6129c (*1) v resetb v reset v ss -0.3 v in +0.3 or +6.5 (*3) v XC6129n (*2) v ss -0.3 +6.5 cd/mrb pin voltage v cd/mrb v ss -0.3 v in +0.3 v cd/mrb pin current i cd/mrb 5 ma power dissipation ssot-24 pd 150 mw uspn-4 100 operating ambient temperature topr -40 +85 storage temperature tstg -55 +125 * all voltages are described based on the v ss . (*1) cmos output (*2) n-ch open drain output (*3) the maximum value should be either v in +0.3 or +6.5 in the lowest. ta = 2 5
8/30 XC6129 series electrical characteristics XC6129xxxa~XC6129xxxf series (output logic: active low) parameter symbol conditions min. typ. max. units circuit detect voltage v df v df(t) (*1) =1.5v 5.5v v df(t) 0.992 v df(t) v df(t) 1.008 v e-1 (*2) temperature characteristics ? v df / ( ? topr ? v df ) -40 Q topr Q 85 - 50 - ppm/ hysteresis width v hys - v df 0.03 v df 0.05 v df 0.07 v supply current 1 i ss1 v in = v df 0.9v (detect) e-2 (*2) a supply current 2 i ss2 v in =v df 1.1v (release) (type:a,c,e) e-3 (*2) (type:b,d,f) e-31 (*2) operating voltage v in - 1.3 - 6.0 v - output current i rbout1 v in =1.3v, v resetb =0.5v (n-ch) 1.7 3.0 - ma v in =2.0v (*3) , v resetb =0.5v (n-ch) 5.2 6.7 - v in =3.0v (*4) , v resetb =0.5v (n-ch) 8.6 10.2 - v in =4.0v (*5) , v resetb =0.5v (n-ch) 10.6 12.3 - v in =5.0v (*6) , v resetb =0.5v (n-ch) 11.7 13.5 - i rbout2 (*7) v in =2.0v (*8) , v resetb =v in -0.5v (p-ch) - -1.9 -0.9 v in =3.0v (*9) , v resetb =v in -0.5v (p-ch) - -3.1 -2.1 v in =4.0v (*10) , v resetb =v in -0.5v (p-ch) - -4.0 -3.0 v in =5.0v (*11) , v resetb =v in -0.5v (p-ch) - -4.7 -3.7 v in =6.0v, v resetb =v in -0.5v (p-ch) - -5.2 -4.2 leakage current cmos output (p-ch) i leak v in =v df 0.9v, v resetb =0v - -0.01 - a n-ch open drain output v in =6.0v, v resetb =6.0v - 0.01 0.1 delay resistance (*12) rp v in =6.0v, v cd/mrb =0v (type: a, b, e, f) 1.8 2.0 2.15 m ? rn v in =v cd/mrb =v df 0.9v (type: c, d, e, f) undefined operation (*13) v uns v in <1.3v - - 0.4 v release delay time t dr0 v in =v df 0.9v v df 1.1v (*14) cd: open - 0.05 - ms detect delay time t df0 v in =v df 1.1v v df 0.9v (*15) cd: open - 0.13 - ms cd threshold voltage v tcd v in =v df 1.1v 6.0v (release) v in 0.44 v in 0.50 v in 0.56 v v in =v df 0.9v (detect) mrb low level voltage v mrl v in =v df 1.1v 6.0v 0 - v in 0.17 v mrb high level voltage v mrh v in =v df 1.1v 6.0v v in 0.56 - v in v minimum mrb pulse width t mrb v in =v df 1.1v v cd/mrb =v in 0v v in 5.0 - - s ta = 2 5 (*1) v df(t) : nominal detect voltage (*2) for the detail value, please refer to ?voltage table?. (*3) for v df(t) 2.0v only (*4) for v df(t) 3.0v only (*5) for v df(t) 4.0v only (*6) for v df(t) 5.0v only (*7) for XC6129c (cmos output) only (*8) for v df(t) Q 1.8v only (*9) for v df(t) Q 2.7v only (*10) for v df(t) Q 3.7v only (*11) for v df(t) Q 4.6v only (*12) resistance is calculated from volt age applied to cd/mrb pin and current. (*13) types b/d/f of XC6129c series only. (*14) time from v in =v df + v hys until v resetb =v df 1.1 0.9 when v in rises. (cmos output) time from v in =v df + v hys until v resetb =pull-up voltage 0.9 when v in rises. (n-ch open drain output) (*15) time from v in =v df until v resetb =v df 0.9 0.1 when v in drops. (cmos output) time from v in =v df until v resetb =pull-up voltage 0.1 when v in drops. (n-ch open drain output)
9/30 XC6129 series electrical characteristics (continued) XC6129xxxg~XC6129xxxl series (output logic: active high) parameter symbol conditions min. typ. max. units circuit detect voltage v df v df(t) (*1) =1.5v 5.5v v df(t) 0.992 v df(t) v df(t) 1.008 v e-1 (*2) temperature characteristics ? v df / ( ? topr ? v df ) -40 Q topr Q 85 - 50 - ppm/ hysteresis width v hys - v df 0.03 v df 0.05 v df 0.07 v supply current 1 i ss1 v in =v df 0.9v (detect) e-2 (*2) a supply current 2 i ss2 v in = v df 1.1v (release) e-3 (*2) operating voltage v in - 1.3 - 6.0 v - output current i rout1 v in =2.0v (*3) , v reset =0.5v (n-ch) 5.2 6.7 - ma v in =3.0v (*4) , v reset =0.5v (n-ch) 8.6 10.2 - v in =4.0v (*5) , v reset =0.5v (n-ch) 10.6 12.3 - v in =5.0v (*6) , v reset =0.5v (n-ch) 11.7 13.5 - v in =6.0v, v reset =0.5v (n-ch) 12.4 14.3 - i rout2 (*7) v in =1.3v, v reset =v in -0.5v (p-ch) - -0.9 -0.1 v in =2.0v (*8) , v reset =v in -0.5v (p-ch) - -1.9 -0.9 v in =3.0v (*9) , v reset =v in -0.5v (p-ch) - -3.1 -2.1 v in =4.0v (*10) , v reset =v in -0.5v (p-ch) - -4.0 -3.0 v in =5.0v (*11) , v reset =v in -0.5v (p-ch) - -4.7 -3.7 leakage current cmos output (p-ch) i leak v in =6.0v, v reset =0v - -0.01 - a n-ch open drain output v in =v df 0.9v, v reset =6.0v - 0.01 0.1 delay resistance (*12) rp v in =6.0v, v cd/mrb =0v (type: g, l) 1.8 2.0 2.15 m ? rn v in = v cd/mrb =v df 0.9v (type: j,l) release delay time t dr0 v in =v df 0.9v v df 1.1v (*13) cd: open - 0.05 - ms detect delay time t df0 v in =v df 1.1v v df 0.9v (*14) cd: open - 0.13 - ms cd threshold voltage v tcd v in =v df 1.1v 6.0v (release) v in 0.44 v in 0.50 v in 0.56 v v in =v df 0.9v (detect) mrb low level voltage v mrl v in =v df 1.1v 6.0v 0 - v in 0.17 v mrb high level voltage v mrh v in =v df 1.1v 6.0v v in 0.56 - v in v minimum mrb pulse width t mrb v in =v df 1.1v v cd/mrb =v in 0v v in 5.0 - - s ta = 2 5 (*1) v df(t) : nominal detect voltage (*2) for the detail value, please refer to ?voltage table?. (*3) for v df(t) Q 1.8v only (*4) for v df(t) Q 2.7v only (*5) for v df(t) Q 3.7v only (*6) for v df(t) Q 4.6v only (*7) for XC6129c (cmos output) only (*8) for v df(t) 2.0v only (*9) for v df(t) 3.0v only (*10) for v df(t) 4.0v only (*11) for v df(t) 5.0v only (*12) resistance is calculated from volt age applied to cd/mrb pin and current. (*13) time from v in =v df + v hys until v resetb =v df 1.1 0.1 when v in rises. (cmos output) time from v in =v df + v hys until v resetb =pull-up voltage 0.1 when v in rises. (n-ch open drain output) (*14) time from v in =v df until v resetb =v df 0.9 0.9 when v in drops. (cmos output) time from v in =v df until v resetb =pull-up voltage 0.9 when v in drops. (n-ch open drain output)
10/30 XC6129 series electrical characteristics (continued) nominal detect voltage e-1 e-2 e-3 e-31 detect voltage (v) supply current1 ( a) supply current2 ( a) v df(t) (v) v df i ss1 i ss2 min. max. min. typ. max. min. typ. max. min. typ. max. 1.5 1.4880 1.5120 - 0.38 1.11 - 0.47 1.39 - 0.63 1.67 1.6 1.5872 1.6128 - 0.42 1.16 - 0.58 1.60 - 0.74 1.88 1.7 1.6864 1.7136 1.8 1.7856 1.8144 1.9 1.8848 1.9152 2.0 1.9840 2.0160 2.1 2.0832 2.1168 2.2 2.1824 2.2176 2.3 2.2816 2.3184 2.4 2.3808 2.4192 2.5 2.4800 2.5200 2.6 2.5792 2.6208 2.7 2.6784 2.7216 2.8 2.7776 2.8224 - 0.47 1.31 - 0.71 1.90 - 0.87 2.18 2.9 2.8768 2.9232 3.0 2.9760 3.0240 3.1 3.0752 3.1248 3.2 3.1744 3.2256 3.3 3.2736 3.3264 3.4 3.3728 3.4272 3.5 3.4720 3.5280 3.6 3.5712 3.6288 3.7 3.6704 3.7296 3.8 3.7696 3.8304 3.9 3.8688 3.9312 4.0 3.9680 4.0320 4.1 4.0672 4.1328 4.2 4.1664 4.2336 - 0.52 1.41 - 0.83 2.17 - 0.99 2.45 4.3 4.2656 4.3344 4.4 4.3648 4.4352 4.5 4.4640 4.5360 4.6 4.5632 4.6368 4.7 4.6624 4.7376 4.8 4.7616 4.8384 4.9 4.8608 4.9392 5.0 4.9600 5.0400 5.1 5.0592 5.1408 5.2 5.1584 5.2416 5.3 5.2576 5.3424 5.4 5.3568 5.4432 5.5 5.4560 5.5440 voltage table ta = 2 5
11/30 XC6129 series test circuits circuit circuit circuit circuit
12/30 XC6129 series test circuits (continued) circuit circuit circuit circuit
13/30 XC6129 series operational description fig. 1: typical circuit (active low product) fig. 2: timing chart of fig. 1 (1) in the initial state, a voltage sufficiently high in relation to the release voltage is applied to the v in power input pin, and the cd/mrb delay capacitance pin is charged to the power input pin voltage. the power input pin voltage starts to drop, and during the interval until it reaches the detect voltage (v in >v df ), the output pin voltage v resetb is at high level. (2) the power input pin voltage continues to drop, and when it reaches the detect voltage (v in =v df ), the nch transistor for delay capacitance discharge turns on and discharge of the delay capacitance starts. when the delay capacitance pin drops below the delay capacitance pin threshold voltage, v resetb changes to low level. the time from v in =v df until v resetb changes to low level is the detect delay t df (the detect time when the delay capacitance pin is open is t df0 ). fig. 1 shows a typical circuit fig. 2 shows the timing chart of fig. 1. * the XC6129n series (n-ch open drain output) requires a resistor to pull up the output. power input voltage: v in release voltage: v df + v hys detect voltage: v df minimum operating voltage (1.3v) delay capacitance pin voltage: v cd/mrb delay capacitance pin threshold voltage: v tcd output pin voltage: v resetb resetb vre f v in cd/ mrb v ss m1 m2 m3 m4 comparator r 1 r 2 rp rn delay/mr control block v dd reset sw cd
14/30 XC6129 series operational description (continued) (3) the power input pin voltage drops further, and during the interval when it is below the detect voltage v df and higher than 1.3v, the delay capacitance pin is discharged to ground level and the output pin voltage v resetb maintains low level. (4) during the interval in which the power input pin voltage drops below 1.3v and then rises ba ck to 1.3v or higher, the output pin voltage v resetb may not be able to maintain low level. operation durin g this interval is called ?unstable operation?, and the voltage that appears in v resetb is called the ?unstable operation voltage v uns ?. (5) the power input pin voltage rises, and during the interval that it is higher than 1.3v until it reaches the release voltage (1.3v v in v df ), the output pin voltage v resetb maintains high level. the above operational explanation is for detection using active low products. for active high products, reverse the logic of v resetb .
15/30 XC6129 series operational description (continued) the release delay time and detect delay time are determined by the delay resistance (rp and rn) and the delay capacitance (cd). the delay resistance is set to 2m ? (typ.) internally in the circuit, and thus the delay time can be changed using the delay capacitance. you can select a product type that has or does not have the release delay time functi on and the detect delay time function. (re fer to the selection guide.) the release delay t dr is calculated using equation (1). t dr =rpcd{-ln(1-v tcd /v in )}+t dr0 ?(1) * ln is the natural logarithm. rn : delay resistance 2.0m ? (typ.) v tcd : delay capacitance pin threshold voltage v in /2 (typ.) when t dr0 can be neglected, this can be calculated in a simple manner using equation (2). t dr =rpcd[-ln{1-(v in /2)/v in }]=rpcd0.693 ?(2) example: when the delay capacitance cd is 0.68 f, the release delay time t dr is 2.010 6 0.6810 -6 0.693=942(ms). the detect delay t df is calculated using equation (3). t df =rncd -ln(v tcd /v in1 )}+t df0 ?(3) * ln is the natural logarithm. rn: delay resistance 2.0m ? (typ.) v tcd : delay capacitance pin threshold voltage v in2 /2 (typ.) *v in2 is the power input pin voltage at detection. v in1 : power input pin voltage at release when v in =v df 1.1v v df 0.9v and t df0 can be neglected, this can be calculated in a simple manner using equation (4). t df =rncd{-ln(v in2 /2)/v in1 }=rncd[-ln{(v df 0.90.5)/(v df 1.1)}]=rncd0.894 ?(4) for details of the detect delay time of equation (4), refer to fig. 3. example: when the delay capacitance cd is 0.68 f at v in =v df 1.1v v df 0.9v, the detect delay time t df is 2.010 6 0.6810 -6 0.894=1216(ms). fig. 3: detect delay time of equation (4) (timing chart) delay time table delay capacitance cd ( f) release delay time t dr (ms) (*1) detect delay time t df (ms) (*1) typ. min.tomax. (*2) typ. min.tomax. (*2) 0.01 13.9 10.4 to 17.7 17.9 12.7 to 22.0 0.022 30.5 22.9 to 38.9 39.3 28.0 to 48.4 0.047 65.1 48.9 to 83.0 84.0 59.8 to 103.3 0.1 139 104 to 177 179 127 to 220 0.22 305 229 to 389 393 280 to 484 0.47 651 489 to 830 840 598 to 1033 1 1386 1042 to 1766 1788 1274 to 2198 the release delay time values are the values calculated from equation (2). the detect delay time values are the values calculated from equation (4). (*1) note that the delay time will vary depending on the ac tual capacitance value of the delay capacitance cd. (*2) the values are calculated with considerat ion given to deviations in the delay resi stance and delay capacitance pin threshold v oltage. power input pin voltage: v in release state (v in1 ) release state (v in1 ) output pin voltage: v resetb delay capacitance pin voltage: v cd/mrb detect delay time: t df delay capacitance pin threshold voltage detect state ( v ss ) v in =v df x 1.1v v in2 =v df x 0.9v v in1 =v df x 1.1v v tcd =v in2 /2=0.9x0.5
16/30 XC6129 series operational description (continued) the reset output pin signal can be forced into the detect state by inputting a voltage into the delay capacitance pin when in t he release state. when the delay capacitance pin voltage input reaches an h l level signal, the reset output pin outputs an h l level signal. (resetb active low type) when the delay capacitance pin voltage input reaches an h l level signal, the reset output pin outputs an l h level signal. (reset active high type) * during manual reset, there is no delay time even when a delay capacitance is connected. * when the delay capacitance pin voltage input reaches an l h level signal in the detection stat e, the reset output pin outputs an l h level signal. (resetb active low type) * when the delay capacitance pin voltage input reaches an l h level signal in the detection stat e, the reset output pin outputs an h l level signal. (reset active high type) under the detect condition, the condition will be k ept even if the reset switch turns on and off. in the case that either h level or l leve l is fed to the cd/mrb pin without the r eset switch, the behavior of the XC6129 follow s the timing chart in fig. 4. l level is fed to the mrb pin under the dete ct condition, the reset switch will be kept. h level is fed to the mrb pin under the detect condition, the reset switch will be undefined. even though the voltage at the v sen pin changes from a higher voltage than the detec t voltage to a lower voltage, as long as h level is fed to the mrb pin, the release condition is kept. if h level or l level is fed to the cd/mrb pin forcibly, then even though cd is connected to t he pin, the XC6129 can?t have any delay time. fig. 4: manual reset operation by the de lay capacitance pin (active low product) types b/d/f of the XC6129c series inclu de an unstable operation prevention function. when the power input pin voltage is less than the minimum operat ion voltage, the output pin voltage due to unstable operation is limited to 0.4v (max.) or less. * types a/c/e of the XC6129c series and each of the XC6129n series do not have an unstable operation prevention function. release voltage:v df +v hys detect voltage:v df mrb high level voltage:v mrh mrb low level voltage:v mrl cd/mrb pin voltage:v cd/mrb (min.:v ss ,max.:v in ) output voltage:v rese tb (min.:v ss ,max.:v in (cmos),v pu l l (nch open drain)) release voltage:v df +v hys detect voltage:v df input voltage:v in min.:0v,max.:6.0v) cd pin threshold voltage:v tcd undefined
17/30 XC6129 series note on use 1) please use this ic within the stated maximum ratings. for te mporary, transitional voltage drop or voltage rising phenomenon, the ic is liable to malfunction should the ratings be exceeded. 2) the power input pin voltage may fall due to the flow through current during ic operation and the resistance component between the power supply and the power input pin. in the case of cmos output, a drop in the power input pin voltage may occur in the same way due to the output current. when this happens, if the power input pin voltage drops below the minimum operating voltage, malfunctioning may occur. in addition, when the power input pin voltage is below the det ect voltage, the output pin voltage may oscillate. exercise caution in particular if a resistor is connected to the power input pin. 3) note that large, sharp changes of the po wer input pin voltage may cause malfunctioning. 4) power supply noise is sometimes a cause of malfunctioning. suff iciently test using the actual device, such as inserting a capacitor between v in and gnd. 5) if a capacitor is connected to the delay capacitance pin and the power input pin voltage drops suddenly during release operatio n (for example, from 6.0v to 0v), there is a possibility that the delay capacitance pin voltage will exceed the absolute maximum ratin g. if there is a possibility that the power input pin voltage will drop suddenly during release operation, connect a schottky diode between the power input pin and delay capacitance pin as shown in fig. 5. fig. 5: circuit example with a schottky di ode connected to the delay capacitance pin 6) when an n-ch open drai n output is used, the v resetb voltage at detection and release is determined by the pull-up resistance connected to the output pin. refer to the fo llowing when selecting the resistance value. at detection: v resetb =v pull /(1+r pull /r on ) v pull : voltage after pull-up r on (*1) : on resistance of n-ch driver m3 (calculated from v resetb /i rbout1 based on electrical characteristics) example: when v in =2.0v (*2) , r on =0.5/5.210 -3 =96 ? (max.). if it is desired to make v resetb at detection 0.1v or less when v pull is 3.0v, r pull =(v pull /v resetb -1)r on =(3/0.1- P 1)96 2.8k ? therefore, to make the output voltage at detection 0.1v or less under the above conditions, the pull-up resistance must be 2.8k ? or higher. (*1) note that r on becomes larger as v in becomes smaller. (*2) for v in in the calculation, use the lowest value of the input voltage range you will use. at release: v resetb =v pull /(1+r pull /r off ) v pull : voltage after pull-up r off : resistance when n-ch driver m3 is off (calculated from v resetb /i leak based on electrical characteristics) example: when v pull is 6.0v, r off =6/(0.110 -6 )=60m ? (min.). if it is desired to make v resetb 5.99v or higher, r pull =(v pull /v resetb -1)r off =(6/5.99-1)6010 6 P 100k ? therefore, to make the output voltage at release 5.99v or higher under the above conditions, the pull-up resistance must be 100k ? or less. (not needed with cmos output)
18/30 XC6129 series note on use (continued) 7) if the discharge time of the delay capacita nce cd at detection is short and the dela y capacitance cd cannot be discharged to ground level, charging will take place at t he next release operation with electric charge remaining in the delay capacitance cd , and this may cause the release delay time to become noticeably short. 8) if the charging time of the delay capacitance cd at release is short and the delay capacitance cd cannot be charged to the v in level, the delay capacitance cd will discharge from less than the v in level at the next detection operation, and this may cause the detect delay time to become noticeably short. 9) even with a non-delay type, a delay time is added when a delay capacitance cd is connected. 10) for a manual reset function, in case when the function is ac tivated by feeding either mrb h level or mrb l level to cd/mrb pin instead of using a reset switch, please note these phenomena below; ? the reset output signal will be undefined when mrb h is fed to cd/mrb pin under the detect condition. ? the reset output signal will be undefined bas ed on the voltage relationship between v sen pin and cd/mrb pin. 11) torex places an importance on improvin g our products and their reliability. we request that users incorporate fail-safe designs and post- aging protection treatment when using torex products in their systems.
19/30 XC6129 series typical performance characteristics (1) detect, release voltage vs. ambient temperature XC6129 (v df(t ) =1.5v) 1.450 1.475 1.500 1.525 1.550 1.575 1.600 -50 -25 0 25 50 75 100 ambient temperature : ta ( ) detect, release voltage : v dfl , v dr (v) v df v dr XC6129 (v df(t ) =2.7v) 2.65 2.70 2.75 2.80 2.85 2.90 -50-250 255075100 ambient temperature : ta ( ) detect, release voltage : v dfl , v dr (v) v dr v df (2) detect, release voltage vs. input voltage XC6129 (v df(t ) =5.5v) 5.40 5.45 5.50 5.55 5.60 5.65 5.70 5.75 5.80 5.85 -50 -25 0 25 50 75 100 ambient temperature : ta ( ) detect, release voltage : v dfl , v dr (v) v dr v df XC6129c (v df(t ) =1.5v) 0 1 2 3 4 5 6 0123456 input voltage : v in (v) output voltage : v resetb (v) ta=- 40 ta=25 ta=85 type : a/c/ e no pull-up : v df : v dr XC6129c (v df(t ) =2.7v) 0 1 2 3 4 5 6 0123456 input voltage : v in (v) output voltage : v resetb (v) ta=- 40 ta=25 ta=85 type : a/c/ e no pull- up : v df : v dr XC6129c (v df(t ) =5.5v) 0 1 2 3 4 5 6 0123456 input voltage : v in (v) output voltage : v resetb (v) ta=-40 ta=25 ta=85 ty pe : a /c/ e no pull-up : v df : v dr
20/30 XC6129 series typical performance characteristics (continued) (2) detect, release voltage vs. input voltage (continued) (3) supply current vs. input voltage XC6129 (v df(t ) =1.5v) 0.00 0.15 0.30 0.45 0.60 0.75 0.90 1.05 1.20 1.35 1.50 0123456 input voltage: v in (v) supply current : i ss ( a) ta=-40 ta=25 ta=85 XC6129 (v df(t ) =2.7v) 0.00 0.15 0.30 0.45 0.60 0.75 0.90 1.05 1.20 1.35 1.50 0123456 input voltage: v in (v) supply current : i ss ( a) ta=-40 ta=25 ta=85 XC6129 (v df(t) =5.5v) 0.00 0.15 0.30 0.45 0.60 0.75 0.90 1.05 1.20 1.35 1.50 0123456 input voltage: v in (v) supply current : i ss ( a) ta=-40 ta=25 ta=85
21/30 XC6129 series typical performance characteristics (continued) (4) supply current vs. ambient temperature XC6129 (v df(t) =1.5v) 0.00 0.15 0.30 0.45 0.60 0.75 0.90 1.05 1.20 1.35 1.50 -50 -25 0 25 50 75 100 ambient temperature : ta ( ) supply current : i ss ( a) detec t release v in =v df 0.9v (detect) v in =v df 1.1v (release) XC6129 (v df(t) =2.7v) 0.00 0.15 0.30 0.45 0.60 0.75 0.90 1.05 1.20 1.35 1.50 -50-25 0 255075100 ambient temperature : ta ( ) supply current : i ss ( a) detec t releas e v in =v df 0.9v (detect) v in =v df 1.1v (release) (5) output current vs. input voltage XC6129 (v df(t) =5.5v) 0.00 0.15 0.30 0.45 0.60 0.75 0.90 1.05 1.20 1.35 1.50 -50 -25 0 25 50 75 100 ambient temperature : ta ( ) supply current : i ss ( a) detec t release v in =v df 0.9v (detect) v in =v df 1.1v (release) XC6129x55a 0 5 10 15 20 25 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 input voltage : vin (v) output current : i rbout (ma) ta=-40 ta=25 ta=85 v resetb =0.5v (nch) XC6129c15a -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 input voltage : vin (v) output current : i rbout (ma) ta=-40 ta=25 ta=85 v reset b =v in -0.5v (pch)
22/30 XC6129 series typical performance characteristics (continued) (5) output current vs. i nput voltage (continued) (6) delay resistance vs. ambient temperature XC6129x 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 -50-250 255075100 ambient temperature : ta ( ) delay resistance : rp (m ? ) v in =6.0v , v cd/mrb =0v (type : a,b,e,f) (7) release delay time vs. ambient temperature XC6129x 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 -50 -25 0 25 50 75 100 ambient temperature : ta ( ) delay resistance : rn (m ? ) v in =v df 0.9v , v cd/mrb =6.0v ( ty pe : c,d,e,f) XC6129 10 11 12 13 14 15 16 17 18 19 20 -50 -25 0 25 50 75 100 ambient temperature : ta ( ) release delay time : t dr (ms) v in =v df 0.9v v df 1.1v cd=0.01 f (t dr =13.9ms) (8) detect delay time vs. ambient temperature XC6129 100 110 120 130 140 150 160 170 180 190 200 -50 -25 0 25 50 75 100 ambient temperature : ta ( ) release delay time : t dr (ms) v in =v df 0.9v v df 1.1v cd=0.1 f (t dr =139ms) XC6129 10 11 12 13 14 15 16 17 18 19 20 -50 -25 0 25 50 75 100 ambient temperature : ta ( ) detect delay time : t df (ms) v in =v df 1.1v v df 0.9v cd=0.01 f (t dr =17.9ms)
23/30 XC6129 series typical performance characteristics (continued) (8) detect delay time vs. ambient temperature (continued) (9) cd pin mrb high level voltage vs. ambient temperature XC6129 100 110 120 130 140 150 160 170 180 190 200 -50 -25 0 25 50 75 100 ambient temperature : ta ( ) detect delay time : t df (ms) v in =v df 1.1v v df 0.9v cd=0.1 f (t dr =179ms) XC6129x 0.0 1.0 2.0 3.0 4.0 -50-25 0 25 50 75100 ambient temperature : ta ( ) mrb highlevel threshold voltage : v mrh (v) v in =6.0v v in =2.0v v in =4.0v (10) cd pin mrb high level voltage vs. input voltage (11) cd pin mrb low level voltage vs. ambient temperature XC6129 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 input voltage : v in (v) mrb highlevel threshold voltage : v mrh (v) ta=-40 ta=25 ta=85 XC6129x 0.0 0.3 0.6 0.9 1.2 1.5 -50 -25 0 25 50 75 100 ambient temperature : ta ( ) mrb lowlevel threshold voltage : v mrl (v) v in =2.0v v in =6.0v v in =4.0v (12) cd pin mrb low level voltage vs. input voltage XC6129 0.00 0.15 0.30 0.45 0.60 0.75 0.90 1.05 1.20 1.35 1.50 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 input voltage : v in (v) mrb highlevel threshold voltage : v mrh (v) ta=-40 ta=25 ta=85
24/30 XC6129 series packaging information unit: mm 0.6 0.25 uspn-4 reference pattern layout uspn-4 reference metal mask design
25/30 XC6129 series ssot-24 power dissipation power dissipation data for the ssot-24 is shown in this page. the value of power dissipation varies with the mount board conditions. please use this data as the reference data taken in the following condition. 1. measurement condition condition: mount on a board ambient: natural convection soldering: lead (pb) free board: dimensions 4040mm (1600mm 2 in one side) copper (cu) traces occupy 50% of the board area in top and back faces package heat-sink is tied to the copper traces material: glass epoxy (fr-4) thickness: 1.6mm through-hole: 4 x 0.8 diameter 2. power dissipation vs. ambient temperature ambient temperature (tjmax=125 ) ambient temperature ( ) power dissipation pd (mw) thermal resistance ( /w) 25 500 200.00 85 200 pd-ta? 0 100 200 300 400 500 600 25 45 65 85 105 125 ??ta S?p?pdmw evaluation board (unit: mm) 40.0 40.0 2.54 2.5 28.9 28.9 1.4 pd vs. ta ambient temperature: ta ( ) power dissipation: pd (mw)
26/30 XC6129 series uspn-4 power dissipation power dissipation data for the uspn-4 is shown in this page. the value of power dissipation varies with the mount board conditions. please use this data as the reference data taken in the following condition. 1. measurement condition condition: mount on a board ambient: natural convection soldering: lead (pb) free board: dimensions 4040mm (1600mm 2 in one side) copper (cu) traces occupy 50% of the front and 50% of the back is 12.5% of total. the copper area is divided into four block, one block is 12.5% of total. the uspn-4 package has for terminals. each terminal connects one copper block in the front and one in the back. material: glass epoxy (fr-4) thickness: 1.6mm through-hole: 4 x 0.8 diameter 2. power dissipation vs. ambient temperature board mount (tjmax=125 ) ambient temperature ( ) power dissipation pd (mw) thermal resistance ( /w) 25 600 166.67 85 240 pd-ta? 0 100 200 300 400 500 600 700 25 45 65 85 105 125 ??ta S?p?pdmw evaluation board (unit: mm) 40.0 2.5 28.9 pd vs. ta ambient temperature: ta ( ) power dissipation: pd (mw)
27/30 XC6129 series marking rule indicates mark (1) product series. indicate s the detect voltage range and output type. mark (1)-1 (XC6129c*****-g is underline mark specification.) mark output detect voltage range (v) type product series 0 cmos odd number a XC6129c15a**-g to XC6129c55a**-g 1 b XC6129c15b**-g to XC6129c55b**-g 2 c XC6129c15c**-g to XC6129c55c**-g 3 d XC6129c15d**-g to XC6129c55d**-g 4 e XC6129c15e**-g to XC6129c55e**-g 5 f XC6129c15f**-g to XC6129c55f**-g 6 g XC6129c15g**-g to XC6129c55g**-g 8 j XC6129c15j**-g to XC6129c55j**-g a l XC6129c15l**-g to XC6129c55l**-g c even number a XC6129c16a**-g to XC6129c54a**-g d b XC6129c16b**-g to XC6129c54b**-g e c XC6129c16c**-g to XC6129c54c**-g f d XC6129c16d**-g to XC6129c54d**-g h e XC6129c16e**-g to XC6129c54e**-g k f XC6129c16f**-g to XC6129c54f**-g l g XC6129c16g**-g to XC6129c54g**-g n j XC6129c16j**-g to XC6129c54j**-g r l XC6129c16l**-g to XC6129c54l**-g mark (1)-2 (XC6129n*****-g is overline mark specification.) mark output detect voltage range (v) type product series 0 n-ch odd number a XC6129n15a**-g to XC6129n55a**-g 1 b XC6129n15b**-g to XC6129n55b**-g 2 c XC6129n15c**-g to XC6129n55c**-g 3 d XC6129n15d**-g to XC6129n55d**-g 4 e XC6129n15e**-g to XC6129n55e**-g 5 f XC6129n15f**-g to XC6129n55f**-g 6 g XC6129n15g**-g to XC6129n55g**-g 8 j XC6129n15j**-g to XC6129n55j**-g a l XC6129n15l**-g to XC6129n55l**-g c even number a XC6129n16a**-g to XC6129n54a**-g d b XC6129n16b**-g to XC6129n54b**-g e c XC6129n16c**-g to XC6129n54c**-g f d XC6129n16d**-g to XC6129n54d**-g h e XC6129n16e**-g to XC6129n54e**-g k f XC6129n16f**-g to XC6129n54f**-g l g XC6129n16g**-g to XC6129n54g**-g n j XC6129n16j**-g to XC6129n54j**-g r l XC6129n16l**-g to XC6129n54l**-g ssot-24 (with overline mark) ssot-24 (with underline mark)
28/30 XC6129 series marking rule (continued) represents detect voltage mark detect voltege(v) mark detect voltege(v) mark detect voltege(v) a 1.5 1.6 k 2.9 3.0 t 4.3 4.4 b 1.7 1.8 l 3.1 3.2 u 4.5 4.6 c 1.9 2.0 m 3.3 3.4 v 4.7 4.8 d 2.1 2.2 n 3.5 3.6 x 4.9 5.0 e 2.3 2.4 p 3.7 3.8 y 5.1 5.2 f 2.5 2.6 r 3.9 4.0 z 5.3 5.4 h 2.7 2.8 s 4.1 4.2 0 5.5 - , represents production lot number 01 09, 0a 0z, 11 9z, a1 a9, aa az, b1 zz repeated. (g i j o q w excluded) * no character inversion used.
29/30 XC6129 series marking rule (continued) uspn-4 represents detect voltage range and product series represents detect voltage mark detect voltege(v) mark detect voltege(v) mark detect voltege(v) a 1.5 1.6 k 2.9 3.0 t 4.3 4.4 b 1.7 1.8 l 3.1 3.2 u 4.5 4.6 c 1.9 2.0 m 3.3 3.4 v 4.7 4.8 d 2.1 2.2 n 3.5 3.6 x 4.9 5.0 e 2.3 2.4 p 3.7 3.8 y 5.1 5.2 f 2.5 2.6 r 3.9 4.0 z 5.3 5.4 h 2.7 2.8 s 4.1 4.2 0 5.5 - , represents production lot number 01 09, 0a 0z, 11 9z, a1 a9, aa az, b1 zz repeated. (g i j o q w excluded) * no character inversion used. represents detect voltage mark output product series k cmos XC6129c*****-g l n-ch XC6129n*****-g mark detect voltage range (v) type product series 0 odd number a XC6129*15a**-g XC6129*55a**-g 1 b XC6129*15b**-g XC6129*55b**-g 2 c XC6129*15c**-g XC6129*55c**-g 3 d XC6129*15d**-g XC6129*55d**-g 4 e XC6129*15e**-g XC6129*55e**-g 5 f XC6129*15f**-g XC6129*55f**-g 6 g XC6129*15g**-g XC6129*55g**-g 8 j XC6129*15j**-g XC6129*55j**-g a l XC6129*15l**-g XC6129*55l**-g c even number a XC6129*16a**-g XC6129*54a**-g d b XC6129*16b**-g XC6129*54b**-g e c XC6129*16c**-g XC6129*54c**-g f d XC6129*16d**-g XC6129*54d**-g h e XC6129*16e**-g XC6129*54e**-g k f XC6129*16f**-g XC6129*54f**-g l g XC6129*16g**-g XC6129*54g**-g n j XC6129*16j**-g XC6129*54j**-g r l XC6129*16l**-g XC6129*54l**-g
30/30 XC6129 series 1. the products and product specifications cont ained herein are subject to change without notice to improve performance characteristic s. consult us, or our representatives before use, to confirm that the informat ion in this datasheet is up to date. 2. we assume no responsibility for any infri ngement of patents, pat ent rights, or other rights arising from the use of any info rmation and circuitry in this datasheet. 3. please ensure suitable shipping controls (including fail-safe designs and aging protection) are in force for equipment employing products listed in this datasheet. 4. the products in this datasheet are not devel oped, designed, or approved for use with such equipment whose failure of malfuncti on can be reasonably expected to directly endanger the life of, or cause significant injury to, the user. (e.g. atomic energy; aerospace; transpor t; combustion and associated safety equipment thereof.) 5. please use the products listed in this datasheet within the specified ranges. should you wish to use the products under conditions exceeding the specifications, please consult us or our representatives. 6. we assume no responsibility for damage or loss due to abnormal use. 7. all rights reserved. no part of this dat asheet may be copied or reproduced without the prior permission of torex semiconductor ltd.

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